1. Field of the Invention
The present invention relates to a disk unit such as a magnetic disk unit or an optical disk unit and more particularly to a clock signal correcting circuit suitable for a so-called "sampled servo system" disk unit in which a plurality of clock marks which provide a timing standard are embedded in data tracks on the surface of the disks beforehand at the time of manufacture.
2. Description of the Prior Art
The construction of one example of a conventional clock generating circuit of the kind to which this invention relates is shown in FIG. 1. The clock generating circuit shown in FIG. 1 is a so-called PLL (Phase Locked Loop) circuit. The PLL circuit 130 comprises a phase comparator 131, a loop filter 132, a VCO (voltage controlled oscillator) 135 and a frequency divider 136. A clock signal reproduced from a disk is supplied to one of the inputs of the phase comparator 131. A clock signal output from the VCO 135 whose frequency is divided by N by the frequency divider 136 is supplied to the other input of the phase comparator 131. The loop filter 132 performs a prescribed filtering process such as lowpass filtering on the output of the phase comparator 131 and supplies its output to the VCO 135. The VCO 135 outputs a clock signal that corresponds to the input voltage. The resulting clock signal output from the VCO 135 is locked to the phase of the reproduced signal from the disk.
The conventional clock generating circuit described above has the following problems in generating accurate clock signals.
(1) A significant phase fluctuation is generated in the clock signal reproduced from the tracks because the effective peripheral velocity fluctuates to the high speed side where the actual track circle radius is large and to the low speed side where the actual track circle radius is small due to an offset, i.e. eccentricity (It is noted that this eccentricity is different than the `eccentricity magnitude` referred to hereinafter; `eccentricity magnitude` refers to a quantity which expresses as a function the phase difference between the clock recorded at predetermined angular positions on the disc, having the home index signal generation position as its reference origin, and the first clock mentioned above.), introduced when the disc is chucked onto the spindle, of the center of the axis of rotation from the center of the track circles. PA1 (2) If the low-pass gain of the PLL loop is increased in order to fully suppress the phase fluctuation caused by the eccentricity, the PLL cannot be made to correctly adapt to the eccentricity of the disk because noise increases in the highpass area due to the widening of the band. PA1 (3) Further, in a memory unit containing a plurality of disk faces, when the disc being accessed is changed over it is difficult to immediately adapt to the eccentricity of the newly accessed disk if the eccentricities of the disks before and after the changeover differ.